This invention relates to clock synchronization circuitry in high speed integrated circuit memory devices. More particularly, this invention relates to clock synchronization circuitry that is turned on only for memory READ operations.
Clock synchronization circuitry is used in high-speed memory devices to reduce phase variations in clock signals. As the speed of memory increases, memory access time decreases. Even small variations in the phase of a clock signal, such as those variations caused by changes in the power, voltage, or temperature of the circuit, can have significant effects on memory access timing. Clock synchronization circuits such as, for example, a delay-locked loop (DLL) circuit can be used to reduce or ideally eliminate these phase variations in the clock signal.
A DLL uses a variable delay line to add phase delay to an input reference clock signal before the signal is output from the DLL. The DLL uses a phase detector to measure the phase difference between the output of the DLL and the reference clock. The variable delay line is then adjusted to obtain the desired phase difference, which is usually zero.
Although clock synchronization circuits make high-speed memory access more reliable by minimizing phase variations in the clock signal, they increase the power consumption of memory devices. Typically, a clock synchronization circuit runs continuously and consumes power even when the synchronized clock signal is not needed. Even in a stand-by or power-down state, when most other memory control logic is turned off to reduce power consumption, the clock synchronization circuitry is typically not turned off. Such circuitry is not turned off because a delay of multiple clock cycles is usually required before a valid synchronized clock signal can be output after the synchronization circuitry is turned on. Thus, the synchronization circuitry is run continuously so that a valid synchronized clock signal is available at all times.
In view of the forgoing, it would be desirable to be able to provide clock synchronization circuitry that only needs to be on when a synchronized clock output is needed (e.g., for high-speed memory READ operations) and that can be turned off when it is not.